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GATE CSE 2026 Session 2 Q57: Speed-up of a pipeline with a slower clock and stalls

Question

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ___________. (rounded off to two decimal places)

Note: 1G=1091\text{G} = 10^9

Try it: numerical answer: type the value

Numerical answer. No negative marking.
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Answer: 2.3 to 2.4 (official GATE 2026 final answer key)

Concept used: Speed-up = (time per instruction, non-pipelined) / (time per instruction, pipelined).

First step: Non-pipelined: 5/1.65 / 1.6 ns; pipelined CPI =1+0.3×2=1.6= 1 + 0.3 \times 2 = 1.6 at 1.2 GHz.

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Source: official GATE 2026 Session 2 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

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