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GATE CSE 2026 Session 1 Q38: Tag length: direct-mapped vs K-way set-associative cache

Question

The size of the physical address space of a processor is 2322^{32} bytes. The capacity of a cache memory unit is 2232^{23} bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a KK-way set-associative cache, where K=2LK = 2^L and L∈{1,2,3}L \in \{1, 2, 3\}. Let the length of the TAG field be MM bits for the direct mapped cache, and NN bits for the set-associative cache.

Which one of the following options is true?

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Answer: A (official GATE 2026 final answer key)

Concept used: Making the cache 2L2^L-way divides the number of sets by 2L2^L, moving LL bits from index to tag.

First step: Direct mapped: 223/27=2162^{23}/2^7 = 2^{16} lines, so index 16 bits; with K=2LK = 2^L ways the set index has 16−L16 - L bits.

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Source: official GATE 2026 Session 1 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

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