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GATE CSE 2026 Session 1 Q15: Instruction sequence for Z = X + Y on a load-store machine

Question

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y ?

Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

Try it: multiple choice: exactly one correct option

Select one option
Wrong answer costs 1/3 mark in GATE.
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Answer: D (official GATE 2026 final answer key)

Concept used: In a load-store ISA only LOAD and STORE access memory; ALU instructions use registers only.

First step: Reject any option where ADD has a memory operand (X, Y or Z).

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Source: official GATE 2026 Session 1 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

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