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GATE CSE 2026 Session 1 Q60: Structural-hazard stall cycles from a multi-cycle EX stage

Question

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let tEXt_{EX} denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of tEXt_{EX} and M (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below.

The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.

InstructiontEXt_{EX} in nanosecondsMM
LOAD1.815
IMUL1.510
IDIV2.55
FADD1.710
FSUB1.75
FMUL2.815
FDIV3.25
All other instructionsLess than 1.035

When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)

Try it: numerical answer: type the value

Numerical answer. No negative marking.
Show answer and explanation

Answer: 95 (official GATE 2026 final answer key)

Concept used: An instruction needing ⌈tEX⌉\lceil t_{EX} \rceil cycles in EX holds the stage for ⌈tEX⌉−1\lceil t_{EX} \rceil - 1 extra cycles.

First step: Extra cycles per instruction: LOAD, IMUL, FADD, FSUB 1 each; IDIV, FMUL 2 each; FDIV 3. Multiply by MM and add.

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Source: official GATE 2026 Session 1 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

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