Skip to content
GATEiit

GATE CSE 2026 Session 1 Q54: Impossible TLB / page table / cache event sequences

Question

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

Try it: multiple select: one or more correct options

Select one or more options
Select all correct options. No negative marking, no partial marks.
Show answer and explanation

Answer: B, C (official GATE 2026 final answer key)

Concept used: The TLB caches valid page-table entries; cache blocks of evicted pages are invalidated.

First step: A TLB hit means the page is resident, so the page table is not even consulted; a page-table miss means the page is not in memory, so its blocks cannot be in the cache.

Full step-by-step solution

Detailed working, common mistakes and linked mock tests will be available with a free GATEiit account. Log-in is coming soon.

Share this question

WhatsAppDownload image

Source: official GATE 2026 Session 1 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

More Computer Organization and Architecture PYQs

PracticePractise Computer Organization and Architecture questions →Full paperAll GATE CSE 2026 Session 1 questions →