GATE CSE 2026 Session 1 Q37: D flip-flop inputs for a 2-bit saturating up/down counter

Digital Logic
2 marks
MCQ
−2/3 if wrong

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.

Input $P$	Current $Q_1$	Current $Q_0$	Next $Q_1^+$	Next $Q_0^+$
0	0	0	0	1
0	0	1	1	0
0	1	0	1	1
0	1	1	1	1
1	0	0	0	0
1	0	1	0	0
1	1	0	0	1
1	1	1	1	0

Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, $D_1$ and $D_0$ ?

Try it: multiple choice: exactly one correct option

Wrong answer costs 2/3 mark in GATE.

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Answer: B (official GATE 2026 final answer key)

Concept used: For D flip-flops, $D_i = Q_i^+$ ; minimise each next-state column with a K-map in $P, Q_1, Q_0$ .

First step: Read the minterms where $Q_1^+ = 1$ : $(P Q_1 Q_0) = 001, 010, 011, 111$ , and test each option's $D_1$ against them.

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Source: official GATE 2026 Session 1 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

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GATE CSE 2026 Session 1 Q37: D flip-flop inputs for a 2-bit saturating up/down counter

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