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GATE CSE 2026 Session 2 Q56: Maximum direct-mapped cache size from an address-to-block mapping

Question

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 17610176_{10}. The maximum possible size of the cache (in KB) for this configuration is ___________. (answer in integer)

Note: 1K=2101\text{K} = 2^{10} and 1M=2201\text{M} = 2^{20}

Try it: numerical answer: type the value

Numerical answer. No negative marking.
Show answer and explanation

Answer: 128 (official GATE 2026 final answer key)

Concept used: Cache block number = (address >> offset bits) mod (number of lines); cache size = 2^(offset + index bits).

First step: Write 0xA2C28 in binary and find the offset width bb for which the bits above it end in 10110000 (= 176), then extend the index over any following 0 bits.

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Source: official GATE 2026 Session 2 CS question paper and final answer key, organised by IIT Guwahati. Question paper · Answer key

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