Skip to content
GATEiit

GATE CSE 2024 Session 2 Q58: Pipeline speedup with data and control hazard stalls

Question

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________

Try it: numerical answer: type the value

Numerical answer. No negative marking.
Show answer and explanation

Answer: 2.9 to 3.1 (official GATE 2024 final answer key)

Concept used: Speedup = non-pipelined CPI / pipelined CPI at the same clock, with CPI = 1 + average stall cycles.

First step: Pipelined CPI =1+0.2×2+0.2×3= 1 + 0.2 \times 2 + 0.2 \times 3.

Full step-by-step solution

Detailed working, common mistakes and linked mock tests will be available with a free GATEiit account. Log-in is coming soon.

Share this question

WhatsAppDownload image

Source: official GATE 2024 Session 2 CS question paper and final answer key, organised by IISc Bangalore. Question paper · Answer key

More Computer Organization and Architecture PYQs

PracticePractise Computer Organization and Architecture questions →Full paperAll GATE CSE 2024 Session 2 questions →