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GATE CSE 2024 Session 1 Q30: Statements about operand forwarding in a 5-stage pipeline

Question

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

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Answer: A, B, C (official GATE 2024 final answer key)

Concept used: Forwarding (bypassing) uses extra paths and multiplexers to avoid data-hazard stalls.

First step: Think of a load followed immediately by an instruction that uses the loaded value.

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Source: official GATE 2024 Session 1 CS question paper and final answer key, organised by IISc Bangalore. Question paper · Answer key

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