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GATE CSE 2023 Q42: Starting addresses of memory blocks selected by IA4 and IA3

Question

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

Ten address lines IA11 to IA5 and IA2 to IA0 (MSB to LSB) form a 10-bit bus to the Addr port of four 1 KB memory blocks X1 to X4. IA4 and IA3 drive inputs A1 and A0 of a 2-to-4 decoder whose outputs Q0, Q1, Q2, Q3 drive the CS inputs of X1, X2, X3, X4
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The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

Try it: multiple choice: exactly one correct option

Select one option
Wrong answer costs 2/3 mark in GATE.
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Answer: C (official GATE 2023 final answer key)

Concept used: The block is chosen by the decoder bits; Addr = 0 means all other address lines are 0.

First step: For each block set IA4 IA3 to its decoder code (00, 01, 10, 11) with all other bits 0, and read the address in decimal.

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Source: official GATE 2023 CS question paper and final answer key, organised by IIT Kanpur. Question paper · Answer key

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