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GATE CSE 2020 Q14: Order of micro-steps for R0 ← R1 + R2 on a single-bus datapath

Question

Consider the following data path diagram.

Single-bus datapath: MAR and MDR connect to memory; IR, PC, registers R0 to R7, TEMP1 feeding one ALU input, the bus feeding the other ALU input, and the ALU output going to TEMP2, which drives the bus
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Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. R2r\text{R2}_r, TEMP1r\text{TEMP1}_r, ALUadd\text{ALU}_{add}, TEMP2w\text{TEMP2}_w

2. R1r\text{R1}_r, TEMP1w\text{TEMP1}_w

3. PCr\text{PC}_r, MARw\text{MAR}_w, MEMr\text{MEM}_r

4. TEMP2r\text{TEMP2}_r, R0w\text{R0}_w

5. MDRr\text{MDR}_r, IRw\text{IR}_w

Which one of the following is the correct order of execution of the above steps?

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Answer: C (official GATE 2020 final answer key)

Concept used: Instruction fetch comes first, then operand transfers through the temporary registers, then write-back.

First step: Fetch is PC to MAR with a memory read (step 3), then MDR to IR (step 5); TEMP1 must be loaded before the ALU adds.

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Source: official GATE 2020 CS question paper and final answer key, organised by IIT Delhi. Question paper · Answer key

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