GATE CSE 2025 Session 2 Q56: Time for 1000 instructions on a 5-stage pipeline with latches
- Computer Organization and Architecture
- 2 marks
- NAT
- No negative marking
Question
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________. (rounded off to two decimal places)
Try it: numerical answer: type the value
Show answer and explanation
Answer: 260.2 to 261.2 (official GATE 2025 final answer key)
Concept used: Clock period = slowest stage + latch delay; instructions on stages take cycles.
First step: Cycle time is ns, and 1000 instructions need cycles.
Full step-by-step solution
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Source: official GATE 2025 Session 2 CS question paper and final answer key, organised by IIT Roorkee. Question paper · Answer key
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