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GATE CSE 2025 Session 1 Q53: Average memory access time with two cache levels

Question

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ________. (rounded off to two decimal places)

Processor connected to L1 cache (hit rate 95%, access time 10 ns), then L2 cache (hit rate 85%, access time including L1 cache miss penalty = 20 ns), then main memory (access time including L1 and L2 cache miss penalty = 200 ns)
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Try it: numerical answer: type the value

Numerical answer. No negative marking.
Show answer and explanation

Answer: 11.83 to 11.87 (official GATE 2025 final answer key)

Concept used: Weighted average of access times over where the access is finally served; here the given times already include the miss penalties.

First step: Served by L1 with probability 0.95, by L2 with 0.05×0.850.05 \times 0.85, by memory with 0.05×0.150.05 \times 0.15; multiply by 10, 20 and 200 ns.

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Source: official GATE 2025 Session 1 CS question paper and final answer key, organised by IIT Roorkee. Question paper · Answer key

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