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GATE CSE 2025 Session 1 Q36: Total tag storage for a direct-mapped 16 KB cache

Question

Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, 1K=2101\text{K} = 2^{10}, 1M=2201\text{M} = 2^{20}.]

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Answer: A (official GATE 2025 final answer key)

Concept used: Direct-mapped address split: tag = address bits − index bits − offset bits; one tag per cache line.

First step: Offset = 4 bits (16-byte blocks), lines = 214/24=2102^{14}/2^4 = 2^{10} so index = 10 bits, leaving 20−1420 - 14 tag bits per line.

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Source: official GATE 2025 Session 1 CS question paper and final answer key, organised by IIT Roorkee. Question paper · Answer key

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