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GATE CSE 2025 Session 1 Q27: Operand combinations supported by a two-mux ALU datapath

Question

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Datapath: Mux_A chooses between register RA and a 32-bit immediate value (Select RA/immediate); Mux_B chooses between register RB and a 32-bit immediate value (Select RB/immediate); both mux outputs feed the ALU, controlled by ALU control lines, whose output goes to register RZ
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Try it: multiple select: one or more correct options

Select one or more options
Select all correct options. No negative marking, no partial marks.
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Answer: A, B, C (official GATE 2025 final answer key)

Concept used: Each ALU input has its own multiplexer, so each operand can independently be a register or an immediate.

First step: List the four select combinations of Mux_A and Mux_B: (RA, RB), (RA, imm), (imm, RB), (imm, imm).

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Source: official GATE 2025 Session 1 CS question paper and final answer key, organised by IIT Roorkee. Question paper · Answer key

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