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GATE CSE 2024 Session 2 Q61: Field widths in R-type and I-type instruction formats

Question

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format
OPCODEUNUSEDDST RegisterSRC Register1SRC Register 2
I-type Instruction Format
OPCODEDST RegisterSRC Register# Immediate value/address

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let XX be the number of bits used to encode the UNUSED field, YY be the number of bits used to encode the OPCODE field, and ZZ be the number of bits used to encode the immediate value/address field. The value of X+2Y+ZX + 2Y + Z is ________

Try it: numerical answer: type the value

Numerical answer. No negative marking.
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Answer: 34 (official GATE 2024 final answer key)

Concept used: Field widths: ⌈log⁡2⌉\lceil \log_2 \rceil of the number of items to encode, with the rest of 32 bits left over.

First step: 50 registers need 6 bits; each type has 75 operations needing 7 bits, plus 1 type bit, so OPCODE is 8 bits.

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Source: official GATE 2024 Session 2 CS question paper and final answer key, organised by IISc Bangalore. Question paper · Answer key

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