Skip to content
GATEiit

GATE CSE 2024 Session 2 Q11: DMA transfer rate with cycle stealing at 1% of cycles

Question

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Try it: multiple choice: exactly one correct option

Select one option
Wrong answer costs 1/3 mark in GATE.
Show answer and explanation

Answer: C (official GATE 2024 final answer key)

Concept used: Cycle stealing: DMA throughput = cycles given to DMA per second × bytes per cycle.

First step: 1% of 4×1064 \times 10^6 cycles/s is 4×1044 \times 10^4 DMA cycles per second, each moving 8 bytes = 64 bits.

Full step-by-step solution

Detailed working, common mistakes and linked mock tests will be available with a free GATEiit account. Log-in is coming soon.

Share this question

WhatsAppDownload image

Source: official GATE 2024 Session 2 CS question paper and final answer key, organised by IISc Bangalore. Question paper · Answer key

More Computer Organization and Architecture PYQs

PracticePractise Computer Organization and Architecture questions →Full paperAll GATE CSE 2024 Session 2 questions →