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GATE CSE 2024 Session 1 Q56: Speedup of a perfect cache given I-cache and D-cache miss rates

Question

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is _________

Try it: numerical answer: type the value

Numerical answer. No negative marking.
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Answer: 3 (official GATE 2024 final answer key)

Concept used: Effective CPI = ideal CPI + memory stall cycles per instruction.

First step: Every instruction is fetched (stall 0.02×1000.02 \times 100) and a quarter access data (stall 0.25×0.08×1000.25 \times 0.08 \times 100).

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Source: official GATE 2024 Session 1 CS question paper and final answer key, organised by IISc Bangalore. Question paper · Answer key

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