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GATE CSE 2022 Q54: Direct-mapped cache behaviour for four repeated data words

Question

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

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Answer: A, B, D (official GATE 2022 final answer key)

Concept used: Split the 16-bit address into tag (5), line index (5) and block offset (6) bits.

First step: Compute (address >> 6) for each word: P and S give block 649 (line 9), Q and R give blocks 778 and 810 (both line 10).

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Source: official GATE 2022 CS question paper and final answer key, organised by IIT Kharagpur. Question paper · Answer key

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