GATE CSE 2025 Session 2 Q31: Output of a NAND, NOT, AND and OR gate circuit
- Digital Logic
- 1 mark
- MSQ
- No negative marking
Question
Consider the following logic circuit diagram.

Which is/are the CORRECT option(s) for the output function ?
Try it: multiple select: one or more correct options
Select all correct options. No negative marking, no partial marks.
Show answer and explanation
Answer: A, B, C (official GATE 2025 final answer key)
Concept used: Read the gate expressions off the diagram, then simplify with absorption and De Morgan's law.
First step: The OR gate receives , and ; both and are already covered by .
Full step-by-step solution
Detailed working, common mistakes and linked mock tests will be available with a free GATEiit account. Log-in is coming soon.
Share this question
Source: official GATE 2025 Session 2 CS question paper and final answer key, organised by IIT Roorkee. Question paper · Answer key
More Digital Logic PYQs
- 2026 Session 1 · Q21Expressions equivalent to (P̄ + Q) ⊕ (P̄Q)
- 2026 Session 1 · Q22Overflow with 8-bit sign-magnitude operands
- 2026 Session 1 · Q37D flip-flop inputs for a 2-bit saturating up/down counter
- 2026 Session 1 · Q48Minimal SOP forms of Σm(1,2,3,4,5,7,10,12,13,14)
- 2026 Session 2 · Q16Which identity is not a law of Boolean algebra
- 2026 Session 2 · Q28Overflow in 4-bit two's complement additions